Christos Kozyrakis' Research

I am broadly interested in Computer Systems Architecture. I am currently involved in projects that explore the architecture, runtime systems, and programming models for highly-parallel systems. In this page, you will find brief descriptions of my current projects, past projects, and some of the chips I have worked on. For the papers related to these projects, please refer to my publications list.

Current Projects

Transactional Coherence and Consistency (TCC): I co-lead the TCC project that aims to simplify parallel programming using transactional memory (TM). With TM, programmers simply request that code segments operating on shared data execute atomically and in isolation with respect to all other code. Concurrency control as multiple transactions execute in parallel is the responsibility of the system. The central idea in TCC is "all transactions, all the time" as, at the hardware-level, there is no execution outside of transactions.  Transactions serve as the fundamental unit of parallel work, communication, synchronization, coherence, consistency, and failure recovery. We are exploring all aspects of TCC and Transactional Memory in general including hardware, prototyping, runtime systems, programming languages, and architectures. If you want a quick introduction to transactional memory in general, check out the slides for the PACT 2006 tutorial.

Architectural Support for Security: The goal of this work is to develop system architectures (hardware + system software) for secure computing. Our initial work has focused on Raksha, a programmable architecture for dynamic information flow tracking. We have developed a full-system prototype for Raksha (Sparc-based processor + Linux OS) that can detect both low-level attacks (e.g., buffer overflows) and high-level attacks (e.g., SQL injections) on unmodified binaries. We are currently pursuing further ideas in hardware and software techniques for security.

Data Center Power Management: The goal of this work is to develop techniques for energy management in data center environments. Our initial work has focused on energy modeling and benchmarking for servers. We have developed Zesti a non-intrusive modeling system that provides accurate estimates of power consumption in a server system using high-level utilization metrics. We have also developed Joulesort, a balanced and system-level benchmark for energy efficiency. Refer to the following links for external discussions on Joulesort (link 1, link 2). 
Smart Memories: I am also affiliated with the Smart Memories project, an effort to develop a general-purpose computing substrate that matches the characteristics of modern VLSI technology and supports a diverse set of computing models. The architecture is based on a single-chip multiprocessor with coarse-grain reconfiguration capabilities, especially in the memory system. Reconfiguration allows Smart Memories to efficiently support streaming, fine-grain multithreaded, and speculatively multithreaded applications on a simple hardware substrate. . 
Old Projects

The following may be "completed" projects, yet the underlying concepts are still of great interest to me.

Cascade: The Cray Cascade project aims at developing a practical PetaFlop supercomputing system for the national security and industrial user community in the 2007 – 2010 timeframe. The effort includes researchers from Cray, Stanford, Caltech, and Notre Dame and is funded by DARPA IPTO within the HPCS program. Our work focuses on two goals. First, we are developing a scalable micro-architecture for a large-scale vector processor. Second, we are exploring flexible architecture support for data-level and thread-level parallelism in large-scale supercomputing systems.

IRAM: The IRAM project developed an embedded processor architecture that combined high multimedia performance, low power consumption, and low design complexity. The key features of the IRAM architectures are vector processing and embedded memory technology. IRAM was mostly  funded by DARPA IPTO within the DIS program.

ATLAS: The ATLAS project developed a single-chip gigabit ATM switch with optional credit-based flow control. The ATLAS switch  is a general-purpose building block for high-speed communication in wide (WAN), local (LAN), and system (SAN) area networking, supporting a mixture of services from real-time, guaranteed quality-of-service to best-effort, bursty and flooding traffic, in a range of applications from telecom to multimedia and multiprocessor NOW. Funding was provided by the European Union.

Telegraphos: The Telegraphos project used RISC principles to develop an architecture for high speed computer communication for workstation clusters. Funding was provided by the European Union

 

Chips and Prototypes

The following are the chips and prototypes I have worked on:

VIRAM Processor (U.C. Berkeley 2003)

Designed in a 0.18um embedded DRAM CMOS process by IBM. This is a media-oriented vector processor with an integrated main memory system. It includes a 64-bit MIPS5Kc processor and a vector coprocessor with 4 lanes. It can reach up to 9.6 Gops/sec at 200MHz and has an on-chip capacity of 13Mbytes. Approximately 125 million transistors in a 324mm2 chip.

VIRAM Test Chip (U.C. Berkeley 1998)

Fabricated by LG in 1998 in a 0.35um embedded DRAM CMOS process. The purpose of this chip was to embedded DRAM with high speed logic and signaling. Approximately 10 million transistors.

ATLAS Switch (ICS/FORTH 1999)

Fabricated by ST in 1999 in a 0.35um CMOS process. This is a 10Gb/s single-chip ATM switch with credit-based flow control and sub-microsecond cut-through latency. Approximately 6 million transistors in a 225mm2 chip.   

 

 

 

TelegraphosII Switch (ICS/FORTH 1995)

Fabricated in 1995 in a 0.7um CMOS process. This is a single-chip switch for distributed shared memory multiprocessors. Approximately 0.6 million transistors in a 72mm 2 chip.